Type or paste a DOI name into the text box. Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development board. In reality, you interesting FPGA board ICARUS learn a lot about FPGAs without ever using real hardware.
As you’ll see, a lot of FPGA development occurs with simulated FPGAs that run on your PC. But if you are like me, blinking a virtual LED just isn’t as exciting as making a real one glow. However, for the first two examples I cover you don’t need any hardware beyond your computer. If you want to get ready, you can order an iCEstick and maybe it’ll arrive before Part III of this series if published. I’m not going to directly try to teach Verilog. However, I will point out a few key areas that trip up new FPGA designers and by following the example code, you’ll be up to speed in no time.
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I just won’t be talking about how to do that. For the FPGA tools used in Part III, I’m using the open source Icestorm tools. I tried using the Lattice tools and it was heartbreakingly difficult to get them installed and licensed. I’ll have more to say about that in part III. We aren’t going to start with a CPU, though. We’ll start with something much more simple.
Let’s Build an Adder There are two main kinds of circuits you build on any FPGA: combinatorial and sequential. The difference is simple: combinatorial logic is all logic gates. The past state of the circuit doesn’t matter. Given a certain set of inputs, the outputs will be the same.
I wanted to show examples of both and how you map them to the board. Verilog Versus Schematic Entry For simple circuits, it is tempting to just draw a schematic like the one above and either machine translate that to the FPGA or hand translate it to Verilog. Some tools support this and you may think that’s the way to go. I know I did when I got started. The truth is, through, that after you move away from simple things, the schematics can be very painful.
For example, think of a seven segment decoder. But it would take a few minutes. If you use Verilog, you can take a simple approach and just write out the gates you want. That will work, but it is usually not the right answer.
Instead, you should describe the circuit behavior you want and the Verilog compiler will infer what circuits it takes to create what you need. The always statement tells Verilog that the code following should execute whenever any of the inputs you use in it change. This infers a combinatorial circuit since there is no clock. You could also use an equal sign here to create a blocking assignment.
For now, the difference doesn’t matter, but we’ll revisit that topic when working with a sequential design. From this description of what you want, the Verilog compiler will infer the right gates and may even be able to perform some optimizations. A key difference between an FPGA and building things on a microcontroller has to do with parallelism. If you wrote similar C code on, say, an Arduino, every copy of it would take some execution time. If you had, for example, 50 decoders, the CPU would have to service each one in turn. With an FPGA, the circuitry that drives each display just works all the time. It isn’t because the FPGA is executing lines of Verilog code or some equivalent structure.
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There is an exception to this. During simulation, Verilog does act like a programming language, but it has very specific rules for keeping the timing the same as it will be on the FPGA. However, it also allows you to write constructs that would not be transferable to the FPGA. For example, a subroutine call doesn’t make sense in hardware, but you can do it during simulation. Look back at the adder schematic. The sum is a simple XOR gate and the carry is an AND gate.
It is smarter, though, to let Verilog figure that out. The braces turn the one bit wires inA and inB into two bit quantities. In this simple example, I might have actually stuck to the first method, but if you think back on the 7 segment decoder, you’ll see it makes sense to use this inferring style where possible. Modules and Definitions When you watch the video below or browse the code, you’ll notice there’s a few minor things I glossed over. For one, all of this code lives in a module. Other modules can create copies of a module and map different signals to its inputs and outputs.
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I wanted to use more meaningful names like inB. A Test Bench Makes The Simulation Possible Before you commit your design to an FPGA, you’ll probably want to simulate it. Debugging is much easier during simulation because you can examine everything. When the Verilog simulator runs, it follows rules about timing that take into account how everything runs at the same time, so the behavior should be exactly what your FPGA will do.
This kind of timing violation is a real problem with large chips and high speeds. For this sort of small circuit, it shouldn’t be an issue. For now, we can assume if the simulation works, the FPGA should behave in the same way. The code will never synthesize, so we can use strange Verilog features that we don’t normally use in our regular code. Note that there is a reg for each input we want to feed the device under test and a wire for each output it will drive.
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That means all of those reg variables need to be set up to our test conditions. Verilog provides an initial block that is usually not valid for synthesis, but will be the main part of most test benches. We’ll be able to examine anything that gets dumped. I didn’t do that in this test.
The next thing you need is some test case stimulus. In the case of the counters, you don’t need anything other than the clock. Without this, the clock generator will cause the simulation to keep going forever. If you want to know more about how it works, check out the video below and I’ll walk through it step by step. Using clocks are an important part of making practical digital designs, as you’ll soon see.
I’ll also have a few more Verilog key points. You can also read the next post in this series. Learning Verilog for FPGAs: Hardware at Last! This is probably the biggest hurdle to overcome when learning FPGAs. Life’s too short to pick up bad habits.
I haven’t talked about clocks yet. Besides, what I’m building here isn’t a counter. I have a few FPGA boards and CPLDs laying around growing a layer of dust I need to get around to playing with. But just thinking about it makes my head spin. BUT the biggest hurdle I have is getting my head around the software you use to program these damn things! Altera Quartus and I’m sure all the rest are beasts to understand, for me anyway. And I’ve used quite a few IDEs.
I got a passing sense of this working with an FPGA guy prototyping an accelerator for elliptic curve cryptography, and it was pretty enlightening. Part of me wishes I could quit my job and do some logic design in anger. Depending on the skill, the block diagram can be more or less detailed. Yes unfortunately with Verilog and VHDL you start in the deep end of the pool. Altera is perhaps the less vicious beast to tame so if your having trouble choosing, then start with Altera.
The truth is that all the IDE’s for this are hard to learn in the beginning. I bought a CPLD kit over 20 years ago and I could never register the software so I gave up, sadly. Also, the trial version of Sigasi is an excelent learning tool. The idea is that you are describing hardware. The Lattice Icestick FOSS toolchain referened in the article is quite easy to use. The Cypress PSoc line has a small programmable logic section that you can target with Verilog.
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I’ve used it to build a quadrature decoder, and other pin driven state machines. Windows just to code for them. I do like the chip, though. Just wish for better tool support on Linux.
I do both, but given a choice I do Verilog. However, the key concepts are the same: you aren’t writing code, you are inferring circuits, etc. According to my TA in university: America uses Verilog, Europe uses VHDL. VHDL is slightly more powerful but slightly more difficult to use. Moore machines scribbled on paper during meetings, so syntax is just implementation.
Now if only I could find a useful application for the Virtex-II that I found in a scrapyard, I’d have a reason to get back into FPGA development. FPGA design in HDL and embedded programming were some of the most enjoyable parts of my EE degree, but the Raspberry Pi came out shortly after I graduated, and I’ve been able to do most of my projects using that. Most projects only get to the demo stage anyway. O ports, two ADCs, two DACs, some DIP switches and LEDs, I’m very interested. The sum is a simple AND gate and the carry is an XOR gate. Al hey your logic is backwards in this statement.
The sum is the XOR gate and the carry is the AND gate. I think you just flipped the roles accidentally. Yep just a slip of the pen. It is right in the Verilog and the drawing. Please, before you start adding in clocks and wondering why things don’t always behave as you expect, you need to be aware of how Verilog processes lines and the use of blocking and non-blocking assignments. Yes, that comes up in the next segment which is already scheduled. The tools will correctly infer the right assignment in a combinatorial block regardless of how you write it, though, especially where there’s only one like this.
You just have to careful not to mix them up, because that can generate some unexpected results, where simulations don’t always agree with hardware. For me, that’s a good reason to try to be consistent, even when it’s not strictly needed. If you want to start looking into performance then you’d be interested to hear that, about 7 years ago, colleagues of mine discovered that if one wrote reset terms for an active low registers ran using ! ICE seems to be verilog biased, all the libs for ICE FPGA are readily available in verilog, for VHDL demos I had to write my own wrappers. I was making test code the the ICEd board, it is by the way mostly compatible to the ICEstick, so many designs for ICEstick also run on ICEd without any changes. Seems a terrible waste just to look like a thumb drive form factor. 144 and next to nothing broken out.
Id there a code fragment missing? That is an artifact of having split the piece into two. So if you look at part 2, you’ll see that part. Al, are you aware of Logisim? It’s an interactive graphical logic simulator, used in a lot of university design courses. It is a wonder no one has forked it and taken it further.
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Hackaday, Hack A Day, and the Skull and Wrenches Logo are Trademarks of Hackaday. When I got my first computer, a second hand 386 running MS-DOS 6. 22, I didn’t have an Internet connection. But I did have QuickBASIC installed and a stack of programming magazines the local library was throwing out, so I had plenty to keep myself busy.
At the time, I thought QuickBASIC was more or less indistinguishable from magic. Unfortunately, that was not to be. Maybe I’m just not well versed enough in DOSBox, but I couldn’t get the IDE to actually run any of the source code I pulled off the floppy. This was disappointing, but then it occured to me that modern BASIC interpreters are probably being developed in some corner of the Internet, and perhaps I could find a way to run my nearly 30 year old code without having to rely on 30 year old software to do it.
Such things were possible with the original QuickBASIC, but existed more in the realm of tech demos than anything else. Oh the games I could have made back in the day with software like this! I had to be content with bleeps and bloops, and even that required you to figure out the timing for the tones yourself. Even better, QB64 is cross-platform and supports compiling into native binaries for Linux, Windows, and Mac OS.