The output signal is a pulse one BCD or Decade Counter-cycle wide occurring at a rate equal to the input frequency divided by N. This single output has TTL drive capability.
The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12. 5, 20, 25, or 50 parts. The first counting section can be preset to 7. The highest count of the various modes is shown in the column entitled Extended Counter Range of Table 1. Control inputs Kb and Kc can be used to initiate and lock the counter in the “master preset” state.
In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kb and Kc both remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. 0 must be applied for at least 3 full clock pulses. A “1” on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to “0”. If the Latch Enable is “0”, the output pulse will remain high for only 1 cycle of the clock-input signal. N” counters are an integral part of the synthesizer phase-locked-loop sub-system.
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The CD4059A can also be used to perform the synthesizer “Fixed Divide-by-R” counting function. Applications Communications digital frequency synthesizers: VHF, UHF, FM, AM, etc. Data sheet acquired from Harris Semiconductor. Understand the operation of synchronous counters.
Describe common control features used in synchronous counters. Use software to simulate counter operation. Counters, consisting of a number of flip-flops, count a stream of pulses applied to the counter’s CK input. The output is a binary value whose value is equal to the number of pulses received at the CK input. Each output represents one bit of the output word, which, in 74 series counter ICs is usually 4 bits long, and the size of the output word depends on the number of flip-flops that make up the counter.
The output lines of a 4-bit counter represent the values 20, 21, 22 and 23, or 1,2,4 and 8 respectively. Four Bit Asynchronous Up Counter Fig. 1 shows a 4 bit asynchronous up counter built from four positive edge triggered D type flip-flops connected in toggle mode. Clock pulses are fed into the CK input of FF0 whose output, Q0 provides the 20 output for FF1 after one CK pulse. CK input of the next flip-flop at half the frequency of the CK pulses applied to its input. 0 will go from 0 to 1.
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Reading the output word from right to left, the Q outputs therefore continue to represent a binary number equalling the number of input pulses received at the CK input of FF0. Four Bit Asynchronous Down Counter To convert the up counter in Fig. 1 to count DOWN instead, is simply a matter of modifying the connections between the flip-flops. By taking both the output lines and the CK pulse for the next flip-flop in sequence from the Q output as shown in Fig. 3, a positive edge triggered counter will count down from 11112 to 00002.
Although both up and down counters can be built, using the asynchronous method for propagating the clock, they are not widely used as counters as they become unreliable at high clock speeds, or when a large number of flip-flops are connected together to give larger counts, due to the clock ripple effect. Clock Ripple The effect of clock ripple in asynchronous counters is illustrated in Fig. As the Q0 to Q3 outputs each change at different times, a number of different output states occur as any particular clock pulse causes a new value to appear at the outputs. At CK pulses other that pulse 8 of course, different sequences will occur, therefore there will be periods, as a change of value ripples through the chain of flip-flops, when unexpected values appear at the Q outputs for a very short time. These short-lived logic values will also cause a series of very short spikes on the Q outputs, as the propagation delay of a single flip-flop is only about 100 to 150ns. 1 value every time, as well as possibly causing false counter triggering, they must also be considered as a possible cause of interference to other parts of the circuit.
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Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a simple and effective frequency divider, where a high frequency oscillator provides the input and each flip-flop in the chain divides the frequency by two. Synchronous Counters The synchronous counter provides a more reliable circuit for counting purposes, and for high-speed operation, as the clock pulses in this circuit are fed to every flip-flop in the chain at exactly the same time. Synchronous counters use JK flip-flops, as the programmable J and K inputs allow the toggling of individual flip-flops to be enabled or disabled at various stages of the count. 5 shows how the clock pulses are applied in a synchronous counter.
Notice that the CK input is applied to all the flip-flops in parallel. Therefore, as all the flip-flops receive a clock pulse at the same instant, some method must be used to prevent all the flip-flops changing state at the same time. This of course would result in the counter outputs simply toggling from all ones to all zeros, and back again with each clock pulse. However, with JK flip-flops, when both J and K inputs are logic 1 the output toggles on each CK pulse, but when J and K are both at logic 0 no change takes place. 6 shows two stages of a synchronous counter.
The binary output is taken from the Q outputs of the flip-flops. On FF1 the J1 and K1 inputs are both connected to Q0 so that FF1 output will only be in toggle mode when Q0 is also at logic 1. In adding a third flip flop to the counter however, direct connection from J and K to the previous Q1 output would not give the correct count. Because Q1 is high at a count of 210 this would mean that FF2 would toggle on clock pulse three, as J2 and K2 would be high.
Therefore clock pulse 3 would give a binary count of 1112 or 710 instead of 410. To prevent this problem an AND gate is used, as shown in Fig. Only when the outputs are in this state will the next clock pulse toggle Q2 to logic 1. 8 shows the additional gating for a four stage synchronous counter. Here FF3 is put into toggle mode by making J3 and K3 logic 1, only when Q0 Q1 and Q2 are all at logic 1. Q3 therefore will not toggle to its high state until the eighth clock pulse, and will remain high until the sixteenth clock pulse. After this pulse, all the Q outputs will return to zero.
Synchronous Down Counter Converting the synchronous up counter to count down is simply a matter of reversing the count. If all of the ones and zeros in the 0 to 1510 sequence shown in Table 5. 8 to the down counter shown in Fig 5. FF0 instead of the Q output.
Each group of gates between successive flip-flops is in fact a modified data select circuit described in Combinational Logic Module 4. This is necessary to provide the correct logic state for the next data selector. FF0, FF1 and FF2 are connected to what are, in effect, the A and B data inputs of the data selectors. BCD Up Counter in Fig 5.
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0 and reset all the flip-flop outputs to logic 0. 0 to 910 and then reset to 0, omitting 1010 to 1510. The circuit is therefore a BCD8421 counter, an extremely useful device for driving numeric displays via a BCD to 7-segment decoder etc. 0 to 15 can be achieved. If you already have a simulator such as Logisim installed on your computer, why not try designing an Octal up counter for example.
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For many applications the counters contained within ICs have extra inputs and outputs added to increase the counters versatility. The differences between many commercial counter ICs are basically the different input and output facilities offered. Some of which are described below. TTL devices any unconnected input would float up to logic 1 and hence become inactive. ICs may have a number of different names, e.
13, is an active low input. JK inputs of all the flip-flops logic 0. When the count is disabled, CTEN and therefore one of the inputs on each of , E1, E2 and E3 will be at logic 0, which will cause these enable gate outputs, and the flip-flop JK inputs to also be at logic 0, whatever logic states are present on the Q outputs, and also at the other enable gate inputs. 0 however, CTEN will be logic 1 and E1, E2 and E3 will be enabled, causing whatever logic state is present on the Q outputs to be passed to the JK inputs. In this condition, when the next clock pulse is received at the CK input the flip-flops will toggle, following their normal sequence. A method of achieving asynchronous parallel loading on a synchronous counter is shown in Fig. This logic 0 is inverted and applied to one input of each of the eight NAND gates to enable them.
If the value to be loaded into a particular flip-flop is logic 1, this makes the inputs of the right hand NAND gate 1,1 and due to the inverter between the pair of NAND gates for that particular input, the left hand NAND gate inputs will be 1,0. This combination sets the Q output to logic 1, the same value that was applied to the D input. Similarly if a D input is at logic 0 the output of the left hand NAND gate of the pair will be Logic 0 and the right hand gate output will be logic 1, which will clear the Q output of the flip-flop. NAND gates, all four flip-flops are loaded simultaneously with the value, either 1 or 0 present at its particular D input. Multiple Inputs and Outputs Modifications such as those described in this module make the basic synchronous counter much more versatile.
Both TTL and CMOS synchronous counters are available in the 74 series of ICs containing usually 4-bit counters with these and other modifications for a wide variety of applications. Allows the count to proceed when at 0. Stops count without resetting when at logic 1. Counts up when 0, down when at logic 1. Q0, Q1, Q2 and Q3 – Four bit binary output. TC can be used to detect the end of an up or down count, and as well as being available as an output, TC is used internally to generate the Ripple Carry output. IC counting the least significant 4 bits, to drive the clock input of the next most significant IC, as show in red in Fig.
TC output is not intended for this purpose, as timing issues can occur. Asynchronous Counters Although synchronous counters have a great advantage over asynchronous or ripple counters in regard to reducing timing problems, there are situations where ripple counters have an advantage over synchronous counters. When used at high speeds, only the first flip-flop in the ripple counter chain runs at the clock frequency. Each subsequent flip-flop runs at half the frequency of the previous one. This can also cause unwelcome spikes on the supply lines that could cause problems elsewhere in the digital circuitry. Asynchronous counters are mostly used for frequency division applications and for generating time delays. In either of these applications the timing of individual outputs is not likely to cause a problem to external circuitry, and the fact that most of the stages in the counter run at much lower frequencies than the input clock, greatly reduces any problem of high frequency noise interference to surrounding components.
74HC393 – Dual 4-stage binary ripple counter from ON Semiconductor. 74HC4040 – 12-Stage binary ripple counter from Fairchild Semiconductor. 74HC93 – 4-Bit binary ripple counter from Texas Instruments. CD4060 – 14-Stage binary counter plus oscillator from ST Microelectronics.