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3.7.2 SDN.702: SDNS Directory Specifications
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To obtain the required accuracy of the six most significant binary weighted bit currents, dynamic element matching is used. 2 – the square root of the number of transistors pairs incorporated in the scaling network. In a 10-bit binary current network the required accuracy between the two MSB currents has to be -3. 1 percent and this implies an offset voltage of 275 µV. The bit switches are optimized for fast-settling and lowglitch current to avoid the need of extra sample-and-hold or deglitcher circuitry. Due to offset-binary coding, the largest glitch occurs at the zero crossing of the analog output signal.
A converter, three different types of switches are used depending on the value of the bit currents to be switched. To avoid differences in base current losses owing to the different bit currents, the six most significant bits are switched with a fast diode-transistor switch, as is shown in Fig. The diode-transistor switch is controlled by data latches and driven by a differential amplifier. During switching transients a small amount of compensation current flows into the output line of the converter. The compensation current in the bit switch has about the same magnitude as the bit current itself. For a sampling period of 5 µs and a transient time of 5 ns this compensation method can be used up to the tenth bit.
To avoid large glitches in the output current this switching method is not used for the six most significant bits. The six least significant bits are switched to the output line with differential pairs, which are compensated for base current losses. A converter at a well-determined level. To allow an easy interfacing between various digital signal processing devices operating at different word lengths, two different data input formats can be used. This standard provides an easy interfacing between digital signal processing devices, operating at various word lengths. In this standard three signals are used. 7 shows the second possible input data format.
In this mode the DATA signals of the left and right channel are applied simultaneously to two different input pins. Only one bit clock signal is used to clock both data signals into the converter. The positive slope of the latch enable signal is used to indicate the end of the data input action and to determine the moment at which the outputs change their sample values. 8 shows a photograph of the dual 16-bit converter. The circuit is processed in a standard bipolar technology with double-sided isolation and double-layer interconnection.
A converter needs a chip area of 3. The output current of the converter is directly fed into the 50-ohm 1-GHz CRT input. Total glitch charge is within 0. 10 shows a block diagram of the test arrangement used for measuring signal-to-noise ratio and total harmonic distortion.
The feedback resistor of the operational amplifier converts the output current of the converter into a voltage and a low-pass output levels. At full scale hardly any decrease in signal-to-noise ratio with respect to the 16-bit theoretical curve is found. 12 shows the signal-to-noise ratio plus the total harmonic distortion as a function of frequency at different output levels. A converter has been realized in a standard bipolar process using a 6-bit dynamic divider and a 10-bit passive divider to construct the binary weighted current network. The combination of the high linearity and the low distortion with the very flexible input format makes the converter very attractive for application in high-performance digital audio equipment such as compact disc players ancl digital tape or cassette recorders. Solid-State Circuits, vol SC-17, pp 1118-1126, Dec.
The bottom 10 bits control transistor switches on the silicon die, each bit switching twice as many transistors as the one below it. 15th LSB two transistors, all the way up to the 10th LSB which switches 512 transistors. Again, they switch transistors controlling currents, but now the sizes of currents are controlled by resistors. Matching is arranged by switching the current-controlling resistors between each transistor switch at a very high frequency. 2 LSBs from bit 1 to bit 16. This grade will be used in inexpensive players and supplied to some third-party manufacturers. A small proportion of DACs meet a more stringent performance standard, having a DLE of less than 0.
5 LSB for bits 1-7, less than 1 LSB for bits 8-15, and less then 0. S” grade and are stamped with a small crown. This top perfoming chip will be used in Philips’s best CD players. Desperation is the Mother of Invention. Isn’t that how the proverb goes? Certainly it applied ten years ago in the case of the Philips engineers working on the development of the Compact Disc system.
Given a specification that had included a 14-bit data word length, they had duly developed a 14-bit DAC chip, the TDA1540, only then to be informed that the CD standard decided upon after Sony joined forces with the Dutch company would involve 16-bit data words. Philips having already committed the 14-bit design to silicon, they would not have a 16-bit DAC ready in time for the medium’s launch in the Fall of 1982. They were thus faced with the problem of squeezing four times the resolution from their existing 14-bit DAC. SAA7321 DAC3 chip massively oversamples the input data at a 256x rate, interpolating the new sample values to produce a 17-bit datastream sampled at 11.
I was told by Philips last year that the Bitstream DAC was therefore intended to be used in low-cost and portable players, the company saying that they would remain with their TD1541-based chip set for high-performance players. A conversion in the preservation of low-level detail. Even Philips has now introduced a Bitstream player, the LHH500. CD players, is also a fascinating topic. In the Red Book, which defines CD standards, the resolution is quoted as being 16 bit. However, the first DAC used in the first Marantz CD player, the Marantz CD-63, and the Philips LHH-2000, was the 14-bit resolution Philips TDA1540. Philips specification would seem inferior, but according to data taken from actual performance situations and among audiophiles with a good ear for sound quality, the performance of the TDA1540 CD player with its 14-bit DAC is rated outstandingly high.
In actual fact, the secret to the excellent sound produced by the Philips SAA7030 digital filter incorporated into the TDA1540 is not obvious at first. The SAA7030 with a 4x over sampling filter capacity utilizes a top quality noise shaping circuit called a secondary noise shaper. Analog filters built into the analog output circuits after the DACs were set for smooth 3rd order slopes with particular attention given to regularity of the phase characteristics. At the time, the filter characteristics of Japanese products were set as high as the 9th or 11th order, and the superb sound quality of the Marantz products was overwhelming. The sound quality of the Marantz CD-34 was given high praise as being nearly equal to that of the ultra high-end Philips LHH-2000.